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RM0008
11.2
ADC main features
Analog-to-digital converter (ADC)
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12-bit resolution
Interrupt generation at End of Conversion, End of Injected conversion and Analog
watchdog event
Single and continuous conversion modes
Scan mode for automatic conversion of channel 0 to channel ‘n’
Self-calibration
Data alignment with in-built data coherency
Channel by channel programmable sampling time
External trigger option for both regular and injected conversion
Discontinuous mode
Dual mode (on devices with 2 ADCs or more)
ADC conversion time:
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STM32F103xx performance line devices: 1 μs at 56 MHz (1.17 μs at 72 MHz)
STM32F101xx access line devices: 1 μs at 28 MHz (1.55 μs at 36 MHz)
STM32F102xx USB access line devices: 1.2 μs at 48 MHz
STM32F105xx and STM32F107xx devices: 1 μs at 56 MHz (1.17 μs at 72 MHz)
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ADC supply requirement: 2.4 V to 3.6 V
ADC input range: V REF- ? V IN ? V REF+
DMA request generation during regular channel conversion
The block diagram of the ADC is shown in Figure 25 .
Note:
11.3
V REF- ,if available (depending on package), must be tied to V SSA .
ADC functional description
Figure 25 shows a single ADC block diagrams and Table 60 gives the ADC pin description.
Doc ID 13902 Rev 9
199/995
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